The present invention relates to an arbiter circuit for settling the competition of two or more request signals.
An arbiter circuit is intended to settle the competition of two or more request signals fed into a specific circuit, and to select any one of the request signals. For example, it is used for the purpose of preventing malfunction of semiconductor memory or destruction of the data by settling the competition of a write request signal and a read request signal for a semiconductor, memory, or competition of a write request signal, a read request signal and a refresh request signal. Two or more request signals may be either synchronized with each other or nonsynchronized.
Recently as video appliances have become more and more advanced in function, their system control has become very difficult. For instance, when using a dynamic random access memory (DRAM) as a field memory in a video tape recorder, writing and reading of data on the DRAM must be done simultaneously, but the DRAM cannot execute writing and reading of data at the same time. Accordingly it is necessary to settle the competition of the write request signal and read request signal to the DRAM so as to carry out either the write request or the read request.
FIG. 9 is a block diagram showing a conventional arbiter circuit, and FIG. 10 is a block diagram showing an RS flip-flop used in the arbiter circuit shown in FIG. 9.
The RS flip-flop in FIG. 10 is composed of first and second NOR gates 100, and 101 respectively possessing two input terminals each. The output terminal of the first NOR gate 100 is connected to one of the input terminals of the second NOR gate 101, while the output terminal of the second NOR gate 101 is connected to one of the input terminals of the first NOR gate 100. To the other input terminals of the first and second NOR gates 100, 101, a reset signal R and a set signal S are supplied respectively. From the first and second NOR gates 100, 101, output signals Q and NQ are delievered.
The RS flip-flop in FIG. 10 has one set input terminal and one, reset input terminal, and hereinafter this is called a 1R-RS flip-flop.
FIG. 9 shows a conventional arbiter circuit using the 1R-RS flip-flop. In FIG. 9 RS flip-flops from a first RS flip-flop 102 to a fourth RS flip-flop 105 are all composed of 1R-RS flip-flops as shown in FIG. 10. A request signal A is fed to the set input terminal S of the first RS flip-flop 102, and a reset signal A is fed to the reset input terminal R of the first RS flip-flop. An output signal A1 of the first RS flip-flop 102 is supplied to one of the input terminals of a first AND gate 106. An output signal A2 of the first AND gate 106 is supplied to the set input terminal S of the second RS flip-flop 103. From a first output terminal Q of the second RS flip-flop 103, an accept signal A is delivered.
A first latch circuit 107 is composed of these first and second RS flip-flops 102, 103 and first AND gate 106.
On the other hand, a second latch circuit 109 is composed of third and fourth RS flip-flops 104, 105 and second AND gate 108. The connecting configuration in the second latch circuit 109 is same as that in the first latch circuit 107. A request signal B is fed to the set input terminal S of the third RS flip-flop 104, while a reset signal B is fed to the reset input terminal R. An accept signal B is delivered from the first output terminal Q of the fourth RS flip-flop 105.
The accept signals A, B are supplied to the input terminals of the NOR gate 110, and the output signal NAB of the NOR gate 110 is supplied to the other input terminals of the first and second AND gates 106, 108.
To the reset input terminals R of the second and fourth RS flip-flops 103, 105, a common request end signal is supplied from an external circuit of the arbiter circuit (for example, a memory block in a DRAM circuit).
FIG. 11 is a timing chart for explaining the basic operation of the arbiter circuit shown in FIG. 9.
FIG. 11 shows potential waveforms of each node when, to the arbiter circuit of FIG. 9,
(1) the request signal A is fed, and after a specific time the reset signal A is fed; PA0 (2) the request signal A is fed and after that the request signal B is fed, then after a specific time the reset signal B is fed; and PA0 (3) either one of the request signal A or B is accepted, and after a specific time the request end signal is fed.
Referring to FIG. 11, the basic operation of the arbiter circuit in FIG. 9 is described below.
In the first place, when the request signal A is supplied to the set input terminal S of the first RS flip-flop 102, the output signal A1 of the first RS flip-flop 102 becomes H level (High) At this time, the accept signals A, B are both at L level (Low) and the output signal NAB of the NOR gate 110 is at H level, and hence the signal of the set input terminal S of the second RS flip-flop 103 becomes H level. As a result, the accept signal A becomes H level, and the request signal A is accepted.
Next, while the accept signal A is at H level, when request signal B is supplied to the set input terminal S of the third RS flip-flop 104, the output signal B1 of the third RS flip-flop 104 becomes H level. In this state, however, since the accept signal A is at H level, the output signal NAB of the NOR gate 110 is at L level. Accordingly, the set input terminal S of the fourth RS flip-flop 105 remains at L level, and the accept signal B also stays at L level.
Upon lapse of a sepcific time after the accept signal A has become H level, when the reset signal A from an external circuti is supplied to the reset input terminal R of the first RS flip-flop 102, the output signal Al is reset and becomes L level. At this timing, however, since the accept signal B is at L level, the reset signal B is not supplied to the reset terminal R of the thrid RS flip-flop 104. As a result, the output signal B1 of the third RS flip-flop 104 remains at H level.
Furthermore, nearly at the same timing as the request signal B, a request end signal from an external circuit is supplied to the reset input terminals R of the second and fourth RS flip-flops 103, 105, and therefore the output signal Q of the second RS flip-flop 103 is reset, and the accept signal A becomes L level. In consequence, the output signal NAB of the NOR gate 110 becomes H level, and the set input terminal S of the fourth RS flip-flop 105 becomes H level, so that the accept signal B changes to H level. Thus, the request signal B is accepted.
According to the arbiter circuit shown in FIG. 9, as described herein, even when request signal B is fed while the accept signal A is at H level by request signal A, the competition of the two request signals A, B is settled, and only one of them can be accepted.
Meanwhile, in the arbiter circuit in FIG. 9, there is no particular problem as far as one request signal (for example A) is accepted, and the other request signal (for example B) is fed after the output signal NAB of the NOR gate 110 is changed to L level, or, to the contrary, the request signal B is first accepted and the other request signal A is fed after the output signal NAB of the NOR gate 110 is changed to L level.
However, if the two request signals A, B are fed almost simultaneously to the arbiter circuit, the disturbance as shown in FIG. 12 takes place. That is, when the request signals A, B are simultaneously fed to the arbiter circuit, the output signals A1, B1 of the first and third RS flip-flops 102, 104 both become H level. At this moment, both accept signals A, B are at L level and the output signal NAB of the NOR gate 110 is at H level, and hence the set input terminals S of the second and fourth RS flip-flops 103, 104 are both at H level, so that both request signal A and request signal B are accepted.
Thus, in the arbiter circuit in FIG. 9, when two request signals A, B are fed nearly at the same time, the intrinsic specification of the arbiter circuit of settling the competition of two requests and selecting one of them is not satisfied.
Moreover, as one request signal A is fed to the arbiter circuit, just before the accept signal A becomes H level and the output signal NAB of the NOR gate 110 becomes L level, if another request signal B is fed to the set input terminal S of the third RS flip-flop 104 and the output signal B1 of the third RS flip-flop 104 becomes H level, such disturbance as shown in FIG. 13 occurs.
That is, right after the output signal B1 of the third RS flip-flop 104 becomes H level, the output signal NAB of the NOR gate 110 becomes L level, and hence the output signal B2 of the second AND gate 108 becomes pulsive. If the pulse width of this pulse is shorter than the delay time from the moment of supply of signal B2 to the set input terminal S of the fourth RS flip-flop 105 until the output signal (accept signal B) is latched, this pulse continues to propagate between two NOR gates 100, 101 (see FIG. 10) in the fourth RS flip-flop 105, and therefore the fourth RS flip-flop 105 oscillates.
To the contrary, as one request signal B is fed to the arbiter circuit, just before the accept signal B becomes H level and the output signal NAB of the NOR gate 110 becomes L level, if the other request signal A is supplied to the set input terminal S of the first RS flip-flop 102 and its output signal Al becomes H level, the output signal (accept signal A) of the second flip-flop 103 oscillates.
It is hence a primary object of the invention to solve such problems and present an arbiter circuit capable of adjusting plural competing request signals even if the plural request signals are substantially fed at the same time, or if the time difference of the plural request signals is very small.